Intel Agilex Configuration User Manual page 75

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
• One JTAG-compatible header connects to several devices in a JTAG chain. The drive capability of the download cable is the
only limit on the number of devices in the JTAG chain.
• If you have four or more devices in a JTAG chain, buffer the
connect other Intel FPGA devices with JTAG support to the chain.
3.4.3.1. JTAG Multi-Device Configuration using Download Cable
Figure 33. Connection Setup for JTAG Multi Device Configuration using Download Cable
Download cable
10-pin male header
(JTAG mode)
Pin 1
Resistor values can vary between 1
Perform signal integrity to select the resistor
Send Feedback
V
CCIO_SDM
10 kΩ
10 kΩ
Intel FPGA
V
CCIO_SDM
nSTATUS
nCONFIG
V
CCIO_SDM
CONF_DONE
MSEL[2:0]
TDI
V
CCIO_SDM
TMS
1 kΩ
GND
kΩ to 10 kΩ.
value for your setup.
, , and
TCK TDI
V
CCIO_SDM
10 kΩ 10 kΩ
Intel FPGA
nSTATUS
nCONFIG
CONF_DONE
MSEL[2:0]
TDI
TDO
TCK TMS TCK
For JTAG configuration only:
Connect MSEL [2:0] of Intel FPGA devices to VCCIO_SDM through 4.7 k
For JTAG in conjunction with another configuration scheme:
Connect MSEL [2:0] of Intel FPGA devices based on the non-JTAG configuration scheme.
pins with an on-board buffer. You can also
TMS
V
CCIO_SDM
10 kΩ 10 kΩ
Intel FPGA
nSTATUS
nCONFIG
CONF_DONE
MSEL[2:0]
TDI
TDO
TDO
TMS TCK
Ω external pull-up resistor.
Intel ® Agilex ™ Configuration User Guide
75