Intel Agilex Configuration User Manual page 49

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
Table 14. PFL II Flash Programming Parameters
Options
Flash programming IP • Area
optimization target
• Speed
Flash programming IP • 16
FIFO size
• 32
Add Block-CRC • On
verification
• Off
acceleration support
Table 15. PFL II FPGA Configuration Parameters
Options
What is the external Provide the frequency of your external clock.
clock frequency?
What is the flash Provide the access time from the flash data sheet.
access time?
What is the byte Provide the byte address of the option bits.
address of the option
bits, in hex?
Which FPGA • Avalon-ST x8
configuration scheme
• Avalon-ST x16
will be used?
• Avalon-ST x32
What should occur on • Halt
configuration failure?
• Retry same page
• Retry from fixed address
Send Feedback
Value
Specifies the flash programming IP optimization. If you optimize the PFL II IP core for
Speed, the flash programming time is shorter, but the IP core uses more LEs. If you
optimize the PFL II IP core for Area, the IP core uses fewer LEs, but the flash
programming time is longer.
Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL
II IP core uses additional LEs to implement FIFO as temporary storage for programming
data during flash programming. With a larger FIFO size, programming time is shorter.
Adds a block to accelerate verification.
Value
Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The
clock frequency must not exceed two times the maximum clock (
the FPGA can use for configuration. The PFL II IP core can divide the frequency of the
input clock maximum by two.
Specifies the flash access time. This information is available from the flash datasheet.
Intel recommends specifying a flash access time that is equal to or greater than the
required time.
For CFI parallel flash, the unit is in ns. For NAND flash, the unit is in μs. NAND flash uses
pages instead of bytes and requires greater access time. This option is disabled for quad
SPI flash.
Specifies the option bits start address in flash memory. The start address must reside on
an 8 KB boundary. This address must be the same as the bit sector address you specified
when converting the
For more information refer to Storing Option Bits.
Specifies the width of the Avalon-ST interface.
Configuration behavior after configuration failure.
Description
Description
to a .
.sof .pof
Intel ® Agilex
) frequency
AVST_CLK
continued...
™ Configuration User Guide
49