Intel Agilex Configuration User Manual page 48

3.1.6.2. PFL II Parameters
Table 12. PFL II General Parameters
Options
What operating mode • Flash Programming
will be used?
• FPGA Configuration
• Flash Programming and FPGA Configuration
What is the targeted • CFI Parallel Flash
flash?
• Quad SPI Flash
Set flash bus pins to • On
tri-state when not in
• Off
use
Table 13. PFL II Flash Interface Setting Parameters
Options
How many flash • 1–16
devices will be used?
What's the largest • 8 Mbit–4 Gbit
flash device that will
be used?
What is the flash • 8
interface data width
• 16
• 32
Allow user to control • On
FLASH_NRESET pin
• Off
Intel ® Agilex ™ Configuration User Guide
48
Value
Specifies the operating mode of flash programming and FPGA configuration control in one
IP core or separate these functions into individual blocks and functionality.
Specifies the flash memory device connected to the PFL II IP core.
Allows the PFL II IP core to tri-state all pins interfacing with the flash memory device
when the PFL II IP core does not require access to the flash memory.
Value
Specifies the number of flash memory devices connected to the PFL II IP core.
Specifies the density of the flash memory device to be programmed or used for FPGA
configuration. If you have more than one flash memory device connected to the PFL II IP
core, specify the largest flash memory device density.
For dual CFI flash, select the density that is equivalent to the sum of the density of two
flash memories. For example, if you use two 512-Mb CFI flashes, you must select CFI 1
Gbit.
Specifies the flash data width in bits. The flash data width depends on the flash memory
device you use. For multiple flash memory device support, the data width must be the
same for all connected flash memory devices.
Select the flash data width that is equivalent to the sum of the data width of two flash
memories. For example, if you are targeting dual solution, you must select 32 bits
because each CFI flash data width is 16 bits.
Creates a
memory device. A low signal resets the flash memory device. In burst mode, this pin is
available by default.
When using a Cypress GL flash memory, connect this pin to the
memory.
Description
Description
pin in the PFL II IP core to connect to the reset pin of the flash
FLASH_NRESET
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
pin of the flash
RESET
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