Intel Agilex Configuration User Manual page 102

Configuration Pin Names (Pre-Intel
Agilex)
MSEL[2]
NSTATUS
NCE
NCEO
(PP32/PP16)
DATA[31:0]
(PP8)
DATA[7:0]
nCSO[2:0]
nIO_PULLUP
AS_DATA0_ASDO
AS_DATA[3:1]
PR_REQUEST
PR_READY
PR_ERROR
PR_DONE
CVP_CONFDONE
Intel ® Agilex ™ Configuration User Guide
102
Intel Agilex Pin Names
( )
SDM_IO9 MSEL[2]
nSTATUS
Not Available
Not Available
AVST_DATA[31:0]
pins ( )
SDM _IO AVSTx8_DATAn
( )
SDMIO_8 AS_nCSO3
( )
SDMI_O7 AS_nCSO2 SDMI_O9
( ) ( )
AS_nCSO1 SDM_IO5 AS_nCSO0
Not Available
( )
SDM_IO4 AS_DATA0
( )
SDM_IO6 AS_DATA3
( )
SDM_IO3 AS_DATA2 SDM_IO1
( )
AS_DATA1
GPIO*
GPIO*
GPIO*
GPIO*
Any unused
SDM_IO CVP_CONFDONE
After the SDM samples , this pin functions as per the configuration mode selected. Do
MSEL
not connect directly to power. Use 4.7 KΩ pull-up or pull-downs, as appropriate.
No longer Open Drain. Intel recommends a 10 KΩ pull-up to V
Multi-device configuration is not supported.
Multi-device configuration is not supported.
Avalon-ST x8 uses SDM pins for data pins.
Intel Agilex supports up to 4 cascaded AS devices
Use a JTAG instruction to invoke.
Unlike earlier device families, the AS interface does not automatically tristate at power-on.
When you set to JTAG, the SDM drives the
MSEL
- , pins until POR.
AS_nCS0 AS_nCS3 MSEL
No dedicated location.
No dedicated location.
No dedicated location.
No dedicated location.
6. Intel Agilex Debugging Guide
UG-20205 | 2019.04.03
Notes
.
CCIO_SDM
, - , and
AS_CLK AS_DATA0 AS_DATA3
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