Intel Agilex Configuration User Manual page 52

Pin
pfl_flash_access_request
flash_addr[]
flash_data[]
flash_nce[]
flash_nwe
flash_noe
flash_clk
flash_nadv
(9)
Intel recommends that you do not insert logic between the PFL II pins and the host I/O pins, especially on the
pins.
fpga_nconfig
Intel ® Agilex ™ Configuration User Guide
52
Type Weak Pull-Up
Output —
Output —
Input or Output —
(bidirectional pin)
Output —
Output —
Output —
Output —
Output —
3. Intel Agilex Configuration Schemes
Function
For system-level synchronization. When necessary, this pin connects to a
processor or an arbiter. The PFL II IP core drives this pin high when the
JTAG interface accesses the flash or the PFL II IP configures the FPGA.
This output pin works in conjunction with the
pins.
The flash memory address. The width of the address bus depends on the
density of the flash memory device and the width of the
Intel recommends that you turn On the Set flash bus pins to tri-state
when not in use option in the PFL II .
Bidirectional data bus to transmit or receive 8-, 16-, or 32-bit data. Intel
recommends that you turn On the Set flash bus pins to tri-state when
(9)
not in use option in the PFL II.
Connects to the pin of the flash memory device. A low signal enables
nCE
the flash memory device. Use this bus for multiple flash memory device
support. The pin connects to each
flash_nce
connected flash memory devices. The width of this port depends on the
number of flash memory devices in the chain.
Connects to the pin of the flash memory device. When low enables
nWE
write operations to the flash memory device.
Connects to the pin of the flash memory device. When low enables
nOE
the outputs of the flash memory device during a read operation.
For burst mode. Connects to the input pin of the flash memory
CLK
device. The active edges of increment the flash memory device
CLK
internal address counter. The
flash_clk
frequency in burst mode for a single CFI flash. In dual CFI flash
pfl_clk
solution, the frequency runs at a quarter of the
flash_clk
frequency. Use this pin for burst mode only. Do not connect these pins
from the flash memory device to the host if you are not using burst mode.
For burst mode. Connects to the address valid input pin of the flash
memory device. Use this signal to latch the start address. Use this pin for
burst mode only. Do not connect these pins from the flash memory device
to the host if you are not using burst mode.
UG-20205 | 2019.04.03
and
flash_noe flash_nwe
bus.
flash_data
pin of all the
nCE
frequency is half of the
pfl_clk
continued...
and
flash_data
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