Hitachi H8/3022 Hardware Manual page 73

Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at
least 7 ms at the system clock rate. For further information about waiting time selection, see
section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.
Bit6 Bit5
STS2 STS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as an interrupt mask bit
1 UI bit in CCR is used as a user bit
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit2
NMIEG Description
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled
Bit4
STS0 Description
0 Waiting time = 8,192 states
1 Waiting time = 16,384 states
0 Waiting time = 32,768 states
1 Waiting time = 65,536 states
0 Waiting time = 131,072 states
1 Waiting time = 1,024 states
— Illegal setting
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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