Table of Contents
Advertisement
TCNT—Timer Counter
Bit
Initial value
Read/Write
RSTCSR—Reset Control/Status Register
Bit
WRST
Initial value
Read/Write
R/(W)
Watchdog timer reset
0 [Clearing condition]
1 [Setting condition]
Note: * Only 0 can be written in bit 7 to clear the flag.
7
6
0
0
R/W
R/W
7
6
RSTOE
0
0
R/W
*
Reset output enable
0 Reset signal is not output externally
1 Reset signal is output externally
Reset signal input at RES pin, or 0 written by software
TCNT overflow generates a reset signal
5
4
0
0
R/W
R/W
Count value
5
4
—
—
1
1
—
—
H'A9 (read),
H'A8 (write)
3
2
0
0
R/W
R/W
H'AB (read),
H'AA (write)
3
2
—
—
1
1
—
—
WDT
1
0
0
0
R/W
R/W
WDT
1
0
—
—
1
1
—
—
609
Advertisement
Table of Contents
