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9.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP
to TP
)* on a bit-by-bit basis.
15
8
Bit
NDER15
Initial value
Read/Write
R/W
If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the
corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not
transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP
Bits 7 to 0
NDER15 to NDER8
0
1
Note: * Since this LSI does not have a TP
292
7
6
NDER14
NDER13
0
0
R/W
R/W
to TP
)* on a bit-by-bit basis.
15
8
Description
TPC outputs TP
(NDR15 to NDR8 are not transferred to PB
TPC outputs TP
(NDR15 to NDR8 are transferred to PB
5
4
NDER12
NDER11
0
0
R/W
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
to TP
are disabled
15
8
to TP
are enabled
15
8
pin, the TP
signal cannot be output to the outside.
14
14
3
2
NDER10
NDER9
0
0
R/W
R/W
to PB
)
7
0
to PB
)
7
0
1
0
NDER8
0
0
R/W
(Initial value)
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