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φ
V
CC
FWE
*1
MD
to MD
2
0
RES
SWE bit
Flash memory access disabled period
(x: Wait time after SWE setting, y: Wait time after SWE clearing)
Flash memory reprogrammable period
(Flash memory program execution and data read, other than verify, are disabled.)
Notes: 1. Always fix the level by pulling down or pulling up the mode pins (MD
until powering off, except for mode switching.
2. See 18.2.5 Flash Memory Characteristics.
t
OSC1
t
MDS
Min.
200 ns
t
MDS
SWE
set
Figure 15-17 Powering On/Off Timing (Boot Mode)
Programming
Wait time:
and erase
x
possible
Wait time:
y
Min. 0 µs
Min. 0 µs
SWE
clear
*2
to MD
2
)
0
479
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