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2. Transitions are made to program mode, erase mode, program-verify mode, and erase-
verify mode according to the settings in this register. When reading flash memory as
normal on-chip ROM, bits 6 to 0 in this register must be cleared.
Bit:
Initial value:
R/W:
Note: * Set according to the state of the FWE pin.
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
Description
0
When a low level is input to the FWE pin (hardware-protected state)
1
When a high level is input to the FWE pin
Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and
erasing. Set this bit when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2.
Bit 6
SWE
Description
0
Writes disabled
1
Writes enabled
[Setting condition]
When FWE = 1
Note: Do not execute a SLEEP instruction while the SWE bit is set to 1.
Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE,
PSU, EV, PV, E, or P bit at the same time.
Bit 5
ESU
Description
0
Erase setup cleared
1
Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
442
7
6
FWE
SWE
—*
0
R
R/W
5
4
ESU
PSU
0
0
R/W
R/W
3
2
EV
PV
0
0
R/W
R/W
1
0
E
P
0
0
R/W
R/W
(Initial value)
(Initial value)
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