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Write pulse application subroutine
Write Pulse subroutine
Enable WDT
Set PSU bit in FLMCR1
) µs
Wait (t
spsu
Set P bit in FLMCR1
200) µs
Wait (t
30 or t
sp
sp
Clear P bit in FLMCR1
) µs
Wait (t
cp
Clear PSU bit in FLMCR1
) µs
Wait (t
cpsu
Disable WDT
End of Subroutine
Note 6: Write Pulse Width
Programming Time (z) µsec
Programming Count (n)
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
.
998
999
1000
Use a 10 µs write pulse for additional programming.
Note:
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming data
storage area (128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of
the first address written to must be H'00 or H'80. A 128-byte data
transfer must be performed even if writing fewer than 128 bytes;
in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the
table below (comparing the data stored in the program data area
with the verify data). For reprogram data 0 bits, programming is
executed in the next reprogramming loop. Therefore, even bits
for which programming has been completed in the 128-byte
programming loop will be subject to programming again if they
fail the subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for
storing reprogram data, and a 128-byte area for storing
additional-programming data must be provided in RAM. The
reprogram and additional-programming data contents are
modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the
progress of the programming operation. See Note 6 for details of
the pulse widths. When writing of additional-programming data is
executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and the value of N are shown in table 18-15, Flash Memory Characteristics.
Reprogram Data Computation Table
Verify Data
Original Data
Reprogram Data
(D)
(V)
(X)
0
0
1
0
1
0
1
0
1
1
1
1
Figure 15-11 H8/3022F Program/Program-Verify Flowchart
464
*7
*5, *7
*7
*7
Increment
t
30
sp
address
t
30
sp
t
30
sp
t
30
sp
t
30
sp
t
30
sp
t
200
sp
t
200
sp
t
200
sp
t
200
sp
t
200
sp
t
200
sp
t
200
sp
.
.
.
t
200
sp
t
200
sp
t
200
sp
Comments
Programming completed
Programming incomplete:
reprogramming to be executed
—
Still in erased state: no action
Start of programming
Start
Set SWE bit in FLMCR1
) µs
Wait (t
sswe
Store 128 bytes of program data in program
data area and reprogram data area
n = 1
m = 0
Successively write 128-byte reprogram
data area in RAM to flash memory
Sub-routine-call
Write Pulse (Write pulse)
Set PV bit in FLMCR1
) µs
Wait (t
spv
H'FF dummy write to verify address
) µs
Wait (t
spvr
Read verify data
Program data =
verify data?
Yes
6 ≥ n?
Yes
Additional-programming data computation
Transfer additional-programming data
to additional-programming data area
Reprogram data computation
Transfer reprogram data to reprogram
data area
128-byte data
verification completed?
No
Yes
Clear PV bit in FLMCR1
) µs
Wait (t
cpv
6 ≥ n?
Yes
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Sub-routine-call
Write Pulse (Additional programming)
m = 0?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
End of programming
Additional-Programming Data Computation Table
Reprogram Data
Verify Data
Additional-Programming
(X')
(V)
0
0
0
1
1
0
1
1
Programming must be executed
in the erased state. Do not
perform additional programming
on addresses that have already
*7
been programmed.
*4
*1
See Note 6 for pulse width
*7
*7
*2
No
m = 1
No
*4
*3
*4
*7
No
*1
*7
No
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
Programming failure
Data (Y)
Additional programming to be executed
0
1
Additional programming not to be executed
1
Additional programming not to be executed
Additional programming not to be executed
1
n ← n + 1
Reprogram
No
*7
Comments
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