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Block Diagrams of Channels 3 and 4: Figure 8-4 is a block diagram of channel 3. Figure 8-5 is a
block diagram of channel 4.
TCLKA to
TCLKD
ø, ø/2,
ø/4, ø/8
Legend
TCNT3:
Timer counter 3 (16 bits)
GRA3, GRB3:
General registers A3 and B3 (input capture/output compare registers)
(16 bits
BRA3, BRB3:
Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits
TCR3:
Timer control register 3 (8 bits)
TIOR3:
Timer I/O control register 3 (8 bits)
TIER3:
Timer interrupt enable register 3 (8 bits)
TSR3:
Timer status register 3 (8 bits)
Clock selector
Comparator
Module data bus
×
2)
×
2)
Figure 8-4 Block Diagram of Channel 3
Control logic
TIOCA
3
TIOCB
3
IMIA3
IMIB3
OVI3
187
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