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Write data delay time
Write data setup time 1
Write data setup time 2
Write data hold time
Read data access time 1
Read data access time 2
Read data access time 3
Read data access time 4
Precharge time
Wait setup time
Wait hold time
Note: * The following times depend on the clock cycle time as shown below.
= 1.5 × t
t
ACC1
cyc
= 2.5 × t
t
ACC2
cyc
= 1.0 × t
t
ACC3
cyc
= 2.0 × t
t
ACC4
cyc
526
– 34 (ns)
t
WSW1
– 34 (ns)
t
WSW2
= 1.0 × t
– 36 (ns)
t
PCH
– 31 (ns)
Symbol
Min
t
—
WDD
t
10
WDS1
t
–10
WDS2
t
20
WDH
t
—
*
ACC1
t
—
*
ACC2
t
—
*
ACC3
t
—
*
ACC4
t
40
*
PCH
t
25
WTS
t
5
WTH
= 1.0 × t
– 24 (ns)
cyc
= 1.5 × t
– 22 (ns)
cyc
– 21 (ns)
cyc
Max
Unit
Test Conditions
55
ns
Figure 18-7,
—
Figure 18-8
—
—
50
105
20
80
—
—
ns
Figure 18-9
—
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