Hitachi H8/3022 Hardware Manual page 215

Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Bit 5—Master Enable TOCXB
Bit 5
EXB4 Description
0 TOCXB
4
input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in
channel 1.
1 TOCXB
4
Bit 4—Master Enable TOCXA
Bit 4
EXA4 Description
0 TOCXA
4
input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
1 TOCXA
4
Bit 3—Master Enable TIOCB
Bit 3
EB3 Description
0 TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB
3
a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCB is enabled for output according to TIOR3 and TFCR settings
3
Bit 2—Master Enable TIOCB
Bit 2
EB4 Description
0 TIOCB output is disabled regardless of TIOR4 and TFCR settings (TIOCB
4
a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCB is enabled for output according to TIOR4 and TFCR settings
4
(EXB4): Enables or disables ITU output at pin TOCXB
4
output is disabled regardless of TFCR settings (TOCXB
is enabled for output according to TFCR settings
(EXA4): Enables or disables ITU output at pin TOCXA
4
output is disabled regardless of TFCR settings (TOCXA
is enabled for output according to TFCR settings
(EB3): Enables or disables ITU output at pin TIOCB
3
(EB4): Enables or disables ITU output at pin TIOCB
4
.
4
operates as a generic
4
(Initial value)
.
4
operates as a generic
4
(Initial value)
.
3
operates as
3
(Initial value)
.
4
operates as
4
(Initial value)
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