Hitachi H8/3022 Hardware Manual page 642

ISR—IRQ Status Register
Bit
Initial value
Read/Write R/W
IRQ
Bits 5, 4, 1 and 0
Note: Only 0 can be written to clear the flag.
*
7 6
— — IRQ5F
0 0
R/W
, IRQ , IRQ and IRQ
5 4 1
IRQ5F
IRQ4F
IRQ1F
IRQ0F Setting and Clearing Conditions
0 [Clearing conditions]
Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
IRQnSC = 0,
handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
1
[Setting conditions]
IRQnSC = 0 and
IRQnSC = 1 and
5 4
IRQ4F
0 0
R/W R/(W) *
flags
0
IRQn input is high, and interrupt exception
IRQn
IRQn
H'F6 Interrupt controller
3 2
— — IRQ1F
0 0
— — R/(W) *
input is low.
input changes from high to low.
(n = 5, 4, 1 and 0)
1 0
IRQ0F
0 0
R/(W) *
633