Item
Write data delay time
Write data setup time 1
Write data setup time 2
Write data hold time
Read data access time 1
Read data access time 2
Read data access time 3
Read data access time 4
Precharge time
Wait setup time
Wait hold time
Note: * The following times depend on the clock cycle time as shown below.
= 1.5 × t
t
ACC1
= 2.5 × t
t
ACC2
= 1.0 × t
t
ACC3
= 2.0 × t
t
ACC4
Symbol
t
WDD
t
WDS1
t
WDS2
t
WDH
t
*
ACC1
t
*
ACC2
t
*
ACC3
t
*
ACC4
t
*
PCH
t
WTS
t
WTH
– 34 (ns)
cyc
– 34 (ns)
cyc
– 36 (ns)
cyc
– 31 (ns)
cyc
Min
Max
—
55
10
—
–10
—
20
—
—
50
—
105
—
20
—
80
40
—
25
—
5
—
= 1.0 × t
t
WSW1
cyc
= 1.5 × t
t
WSW2
cyc
= 1.0 × t
t
– 21
PCH
cyc
Unit
Test Conditions
ns
Figure 18-7,
Figure 18-8
Figure 18-9
– 24
(ns)
– 22
(ns)
(ns)
515