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SYSCR—System Control Register
Bit
SSBY
Initial value
Read/Write
R/W
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
630
7
6
STS2
STS1
0
0
R/W
R/W
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6
Bit 5
STS2
STS1
0
0
1
1
0
1
5
4
STS0
UE
0
0
R/W
R/W
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
Bit 4
STS0
Standby Timer
0
Waiting time = 8192 states
1
Waiting time = 16384 states
0
Waiting time = 32768 states
1
Waiting time = 65536 states
—
Waiting time = 131072 states
—
Illegal setting
H'F2
3
2
NMIEG
1
0
R/W
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled
System control
1
0
—
RAME
1
1
—
R/W
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