Hitachi H8/3022 Hardware Manual page 194

 Complementary PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
non-overlapping complementary waveforms.
 Buffering
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
• High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
• Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
• Output triggering of programmable pattern controller (TPC)
Compare match/input capture signals from channels 0 to 3 can be used as TPC output triggers.
Table 8-1 summarizes the ITU functions.
Table 8-1 ITU Functions
Item
Clock sources
General registers
(output
compare/input
capture registers)
Buffer registers
Input/output pins
Output pins
Counter clearing
function
182
Channel 0 Channel 1
I nter nal cl ock s : ø , ø/ 2, ø/ 4, ø/ 8
Ex ter nal cl ock s : TCLKA, TCLKB, TCLKC, TCLKD, selectable
independently
GRA0, GRA1,
GRB0 GRB1
— —
TIOCA , TIOCA
0
TIOCB TIOCB
0
— —
GRA0/ GRB0 GRA1/ GRB1
compare compare
match or match or
input input
capture capture
Channel 2
GRA2,
GRB2
—
, TIOCA ,
1 2
TIOCB
1 2
—
GRA2/ GRB2
compare
match or
input
capture
Channel 3 Channel 4
GRA3, GRA4,
GRB3 GRB4
BRA3, BRA4,
BRB3 BRB4
TIOCA , TIOCA
3
TIOCB TIOCB
3
— TOCXA
TOCXB
GRA3/ GRB3 GRA4/ GRB4
compare compare
match or match or
input input
capture capture
,
4
4
,
4
4