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Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
1
M = | ( 0.5 –
)– (L – 0.5) F
2N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
When D = 0.5, F = 0:
M = [0.5 – 1/(2 × 16)] × 100%
= 46.875% ........................................................................... (2)
This is a theoretical value. A reasonable margin to allow in system design is 20% to 30%.
Restrictions in Synchronous Mode: When data transmission is performed using an external
clock source as the serial clock, an interval of at least 5 states is necessary between clearing the
TDRE bit in SSR and the start (falling edge) of the first transmit clock pulse corresponding to each
frame (figure 11-22). This interval is also necessary when performing continuous transmission. If
this condition is not satisfied, an operation error may occur.
380
16 clocks
8 clocks
0
7
Start bit
| D – 0.5 |
N
15 0
(1 + F) | × 100% .............(1)
7
15 0
D
0
D
1
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