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External clock source
Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and
its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling
edge, or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter
pulses will not be counted correctly.
Figure 8-18 shows the timing when both edges are detected.
ø
External
clock input
TCNT input
TCNT
Figure 8-18 Count Timing for External Clock Sources (when Both Edges are Detected)
226
N – 1
N
N + 1
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