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Increment
address
Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.
2. Verify data is read in 16-bit (word) units.
3. Set only one bit in the erase block register (EBR1/EBR2). More than one bit must not be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
5. The wait times and the value of N are shown in table 18-15, Flash Memory Characteristics.
466
Start
Set SWE bit in FLMCR1
Wait (t
sswe
n = 1
Set EBR1 or EBR2
Enable WDT
Set ESU bit in FLMCR1
Wait (t
sesu
Set E bit in FLMCR1
Wait (t
) ms
se
Clear E bit in FLMCR1
) µs
Wait (t
ce
Clear ESU bit in FLMCR1
Wait (t
cesu
Disable WDT
Set EV bit in FLMCR1
Wait (t
sev
Set block start address to verify address
H'FF dummy write to verify address
Wait (t
sevr
Read verify data
Verify data = all "1"?
Yes
No
Last address of block?
Yes
Clear EV bit in FLMCR1
Wait (t
cev
*4
End of
No
erasing of all erase
blocks?
Yes
Clear SWE bit in FLMCR1
Wait (t
cswez
End of erasing
Figure 15-12 H8/3022F Erase/Erase-Verify Flowchart
*1
) µs
*5
*3
) µs
*5
Start erase
*5
Halt erase
*5
) µs
*5
) µs
*5
) µs
*5
*2
No
) µs
*5
) µs
*5
Erasing must be performed
in block units.
Clear EV bit in FLMCR1
) µs
Wait (t
cev
*5
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
) µs
Wait (t
cswe
Erase failure
n ← n + 1
*5
Re-erase
No
*5
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