Table of Contents
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13.2.3 A/D Control Register (ADCR).............................................................................. 415
13.3 CPU Interface ..................................................................................................................... 416
13.4 Operation ............................................................................................................................ 417
13.4.1 Single Mode (SCAN = 0)...................................................................................... 417
13.4.2 Scan Mode (SCAN = 1) ........................................................................................ 419
13.4.3 Input Sampling and A/D Conversion Time .......................................................... 421
13.4.4 External Trigger Input Timing .............................................................................. 422
13.5 Interrupts ............................................................................................................................ 423
13.6 Usage Notes .......................................................................................................................... 423
14.1 Overview ............................................................................................................................ 429
14.1.1 Block Diagram ...................................................................................................... 430
14.1.2 Register Configuration .......................................................................................... 430
14.2 System Control Register (SYSCR) .................................................................................... 431
14.3 Operation ............................................................................................................................ 432
15.1 Features .............................................................................................................................. 433
15.2 Overview ............................................................................................................................ 434
15.2.1 Block Diagram ...................................................................................................... 434
15.2.2 Mode Transitions .................................................................................................. 435
15.2.3 On-Board Programming Modes............................................................................ 436
15.2.4 Flash Memory Emulation in RAM........................................................................ 438
15.2.5 Differences between Boot Mode and User Program Mode .................................. 439
15.2.6 Block Configuration.............................................................................................. 440
15.3 Pin Configuration ............................................................................................................... 440
15.4 Register Configuration ....................................................................................................... 441
15.5 Register Descriptions.......................................................................................................... 441
15.5.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 441
15.5.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 444
15.5.3 Erase Block Register 1 (EBR1) ............................................................................ 445
15.5.4 Erase Block Register 2 (EBR2) ............................................................................ 446
15.5.5 RAM Emulation Register (RAMER).................................................................... 447
15.5.6 Differences from H8/3039 F-ZTAT Series ........................................................... 449
15.6 On-Board Programming Modes ......................................................................................... 450
15.6.1 Boot Mode............................................................................................................. 451
15.6.2 User Program Mode .............................................................................................. 456
15.7 Programming/Erasing Flash Memory ................................................................................ 458
15.7.1 Program Mode....................................................................................................... 459
15.7.2 Program-Verify Mode ........................................................................................... 460
15.7.3 Notes on Program/Program-Verify Procedure...................................................... 460
15.7.4 Erase Mode............................................................................................................ 465
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.................................................................................................................... 429
.................................................................................................................... 433
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