Hitachi H8/3022 Hardware Manual page 594

TMDR—Timer Mode Register
Bit
Initial value
Read/Write
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
7 6
— MDF FDIR
1 0
— R/W R/W
PWM mode 2
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
5 4 3
PWM4 PWM3
0 0 0
R/W R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
H'62 ITU (all channels)
2 1
PWM2 PWM1 PWM0
0 0
R/W R/W
0
0
R/W
585