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NDERB—Next Data Enable Register B
Bit
NDER15
Initial value
Read/Write
Next data enable 15 to 8
NDER15 to NDER8
Note: * Since this LSI does not have a TP
NDERA—Next Data Enable Register A
Bit
NDER7
Initial value
Read/Write
Next data enable 7 to 0
7
6
NDER14
NDER13
0
0
R/W
R/W
Bits 7 to 0
0
1
7
6
NDER6
NDER5
0
0
R/W
R/W
Bits 7 to 0
NDER7 to NDER0
0
1
5
4
NDER12
NDER11
0
0
R/W
R/W
Description
TPC outputs TP
to TP * are disabled
15
(NDR15 to NDR8 are not transferred to PB to PB )
TPC outputs TP
to TP * are enabled
15
(NDR15 to NDR8 are transferred to PB to PB )
pin, the TP
14
5
4
NDER4
NDER3
0
0
R/W
R/W
Description
TPC outputs TP to TP are disabled
7
(NDR7 to NDR0 are not transferred to PA to PA )
TPC outputs TP to TP are enabled
7
(NDR7 to NDR0 are transferred to PA to PA )
H'A2
3
2
NDER10
NDER9
0
0
R/W
R/W
8
8
signal cannot be output off-chip.
14
H'A3
3
2
NDER2
NDER1
0
0
R/W
R/W
0
0
7
TPC
1
0
NDER8
0
0
R/W
R/W
7
0
7
0
TPC
1
0
NDER0
0
0
R/W
R/W
7
0
0
605
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