Table of Contents
Advertisement
2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets this set to 1, the CPU sets the I bit in the condition code
register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition
code register to 1. Then the CPU fetches a start address from the exception vector table and
execution branches to that address.
Figure 2-14 shows the stack after the exception-handling sequence.
SP–4
SP–3
SP–2
SP–1
SP (ER7)
Legend
CCR:
Condition code register
SP:
Stack pointer
Notes: 1.
PC is the address of the first instruction executed after the return from the
exception-handling routine.
2.
Registers must be saved and restored by word access or longword access,
starting at an even address.
50
Stack area
Before exception
handling starts
Figure 2-14 Stack Structure after Exception Handling
SP (ER7)
SP+1
SP+2
SP+3
SP+4
Pushed on stack
CCR
PC
After exception
handling ends
Even
address
Advertisement
Table of Contents
