Table of Contents
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9.2.3
Port B Data Direction Register (PBDDR) ............................................................ 286
9.2.4
Port B Data Register (PBDR)................................................................................ 286
9.2.5
Next Data Register A (NDRA) ............................................................................. 287
9.2.6
Next Data Register B (NDRB).............................................................................. 289
9.2.7
Next Data Enable Register A (NDERA)............................................................... 291
9.2.8
Next Data Enable Register B (NDERB) ............................................................... 292
9.2.9
TPC Output Control Register (TPCR) .................................................................. 293
9.2.10 TPC Output Mode Register (TPMR) .................................................................... 296
9.3
Operation ............................................................................................................................ 298
9.3.1
Overview ............................................................................................................... 298
9.3.2
Output Timing ....................................................................................................... 299
9.3.3
Normal TPC Output .............................................................................................. 300
9.3.4
Non-Overlapping TPC Output .............................................................................. 302
9.4
Usage Notes........................................................................................................................ 305
9.4.1
Operation of TPC Output Pins .............................................................................. 305
9.4.2
Note on Non-Overlapping Output......................................................................... 305
10.1 Overview ............................................................................................................................ 307
10.1.1 Features ................................................................................................................. 307
10.1.2 Block Diagram ...................................................................................................... 308
10.1.3 Pin Configuration .................................................................................................. 308
10.1.4 Register Configuration .......................................................................................... 309
10.2 Register Descriptions.......................................................................................................... 310
10.2.1 Timer Counter (TCNT) ......................................................................................... 310
10.2.2 Timer Control/Status Register (TCSR) ................................................................. 311
10.2.3 Reset Control/Status Register (RSTCSR) ............................................................. 313
10.2.4 Notes on Register Access...................................................................................... 315
10.3 Operation ............................................................................................................................ 317
10.3.1 Watchdog Timer Operation .................................................................................. 317
10.3.2 Interval Timer Operation ...................................................................................... 318
10.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 319
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 320
10.4 Interrupts ............................................................................................................................ 321
10.5 Usage Notes........................................................................................................................ 321
11.1 Overview ............................................................................................................................ 323
11.1.1 Features ................................................................................................................. 323
11.1.2 Block Diagram ...................................................................................................... 325
11.1.3 Pin Configuration .................................................................................................. 326
11.1.4 Register Configuration .......................................................................................... 326
11.2 Register Descriptions.......................................................................................................... 327
vi
.............................................................................................. 307
................................................................. 323
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