Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478 CPU Specification
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Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478 CPU Specification

Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478 CPU Specification

Celeron processor in the 478-pin package, specification update
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R
®
Intel
Celeron
478-Pin Package
Specification Update
October 2006
®
Notice: The Intel
Celeron
defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are documented in this
Specification Update.
®
Processor in the
®
Processor in the 478-Pin Package may contain design
Document Number: 290749-030

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Summary of Contents for Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478 CPU

  • Page 1 Specification Update October 2006 ® ® Notice: The Intel Celeron Processor in the 478-Pin Package may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Celeron Pentium, Intel Xeon, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

  • Page 3: Table Of Contents

    Summary Tables of Changes ..................... 8 General Information ......................14 Component Identification Information ................15 Errata..........................19 Specification Changes ...................... 46 Specification Clarifications ....................47 Documentation Changes ....................50 § ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...

  • Page 4: Revision History

    -003 Added erratum AC37. Added Documentation Changes AC3- AC12. July 2002 ® ® -004 Updated with Intel Celeron Processor on 0.13 Micron Process and in September the 478-Pin Package. Added erratum AC38. Updated Erratum AC17. 2002 Added Documentation Changes AC3- AC24.
  • Page 5 • Added erratum AC69. Updated Summary Table of Changes. -029 June 2006 • Updated the names of the Software Developer Manuals. Updated -030 October 2006 Summary Table of Changes. Updated Links. ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...

  • Page 6: Preface

    Package /processors/celeron/478/ Related Documents Document Title Document Number Intel® 64 and IA-32 Intel® Architectures Software Developer's 253665 Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Intel® Architectures Software Developer's 253666 Manual, Volume 2A: Instruction Set Reference, A-M Intel® 64 and IA-32 Intel® Architectures Software Developer's...
  • Page 7 Care should be taken to read all notes associated with each S-Spec number ® ® Errata are design defects or errors. Errata may cause the Intel Celeron processor in the 478-pn package behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 8: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications, or Documentation Changes that apply to the listed component steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 9 4 processor supporting Hyper-Threading Technology on 90- nm process technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon™ processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor-M V = Mobile Intel®...
  • Page 10 Incorrect data may be returned when page tables are in Write AC25 Fixed Combining (WC) memory space AC26 PlanFix Buffer on resistance may exceed specification Processor issues inconsistent transaction size attributes for AC27 NoFix locked operation ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 11 Segment (TSS) May be Incorrect Changes to CR3 Register do not Fence Pending Instruction AC47 NoFix Page Walks Processor Provides a 4-Byte Store Unlock After an 8-Byte AC48 NoFix Load Lock ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 12 Using 2M/4M Pages When A20M# Is Asserted May Result in AC67 NoFix Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line AC68 NoFix without Proper Semaphores or Barriers May Expose a Memory Ordering Issue ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 13 AC69 NoFix Flags May be set Incorrectly SPECIFICATION CHANGES No update for this Month SPECIFICATION CLARIFICATIONS No Update for this month. DOCUMENTATION CHANGES Refer to Documentation Changes section § ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...

  • Page 14: General Information

    General Information General Information ® ® This section contains top marking information for the Intel Celeron processor in the 478-pn package. ® ® Figure 1. Example Markings for the Intel Celeron Processor on 0.13 Micron Process and/or in the 478-Pin Package ©...

  • Page 15: Component Identification Information

    3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a 1 in the EAX register. ® ® Table 1. Intel Celeron Processor in the 478-Pin Package Processor Identification Information L2 Cache...
  • Page 16 Component Identification Information ® ® Table 1. Intel Celeron Processor in the 478-Pin Package Processor Identification Information L2 Cache Core Size Processor Package and S-Spec Stepping (bytes) Signature Speed Core/Bus Revision Notes SL6RV 128K 0F27h 2 GHz/ FC-PGA2 4, 8, 9 400 MHz 31.0 mm , rev...
  • Page 17 Component Identification Information ® ® Table 1. Intel Celeron Processor in the 478-Pin Package Processor Identification Information L2 Cache Core Size Processor Package and S-Spec Stepping (bytes) Signature Speed Core/Bus Revision Notes SL6W2 128K 0F29h 2.20 GHz/ FC-PGA2 2, 6, 8 400 MHz 31.0 mm , rev...
  • Page 18 Component Identification Information ® ® Table 1. Intel Celeron Processor in the 478-Pin Package Processor Identification Information L2 Cache Core Size Processor Package and S-Spec Stepping (bytes) Signature Speed Core/Bus Revision Notes SL6VV 128K 0F27h 2.60 GHz/ FC-PGA2 8, 11 400 MHz 31.0 mm , rev...

  • Page 19: Errata

    Workaround: Ensure that PWRGOOD remains asserted throughout any RESET# assertion and that RESET# is not re-asserted while PWRGOOD is de-asserted. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 20 Some invalid opcodes require a ModRM byte (or other following bytes), while others do not. The Problem: invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel® architecture processors, but does in the Intel® Pentium® 4 processor.
  • Page 21 This erratum may result in some performance degradation when using no-fill mode with large Implication: pages. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 22 When this erratum occurs the overflow bit will not be set. Implication: Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 23 When this erratum occurs, the IA32_MC1_STATUS register will contain incorrect information Implication: for correctable errors. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 24 UC load will reduce the occurrence of this erratum. Implication: Certain debug mechanisms do not function as expected on the processor. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 25 Implication: The processor is unable to correctly report and/or recover from certain errors. Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 26 The performance counters do not cascade when the FORCE_OVF bit is set. Implication: Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 27 The processor will go into a sleep state from which it fails to return. Implication: Workaround: Use a duty cycle other than 12.5% or 25%. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 28 Implication: Workaround: The chipset could issue a BIL (snoop) to the deferred processor to eliminate the failure conditions. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 29 Data Translation Look-Aside Buffer, an unintended UnCacheable load operation may be sent out on the system bus. When this erratum occurs, an unintended load may be sent on system bus. Intel has only Implication: encountered this erratum during pre-silicon simulation.
  • Page 30 When this erratum occurs, the processor will hang. Implication: Workaround: The system BIOS should prevent the processor from going to the Deep Sleep state. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 31 Workaround: Ignore any information in the IA32_MC0_ADDR and IA32_MC0_MISC registers after a data, address or response parity error. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 32 CR2 and the error code pushed on the stack are reflective of the speculative state. Intel has not observed this erratum with commercially available software. When this erratum occurs, the contents of CR2 may be off by two, or an incorrect page fault error Implication: code may be pushed onto the stack.
  • Page 33 7. The writeback from the WC Buffers completes leaving stale data, for cacheline A, in the Exclusive (E) state in the L2 cache. Stale data may be consumed leading to unpredictable program execution. Intel has not been able Implication: to reproduce this erratum with commercial software.
  • Page 34 This will force the store to the APIC register before any subsequent instructions are executed. No commercial operating system is known to be impacted by this erratum. For the steppings affected, see the Summary Tables of Changes Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 35 If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the Problem: processor may hang while trying to evict the line. If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any Implication: commercially available software Workaround: None For the steppings affected, see the Summary Tables of Changes.
  • Page 36 This erratum has not been observed in commercially available software. Workaround: None For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 37 APIC will complete the operation so as not to hang the processor. The processor may hang. Implication: Workaround: None identified. For the steppings affected, see the Summary Tables of Changes Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 38 Implication: Workaround: Execution after the break will continue, if you manually clear DR7 bit 1 (Global Breakpoint Enable). For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 39 The actual value could be as high as 800 mV. The PWRGOOD and TAP inputs may switch at different levels than previously documented Implication: specifications. Intel has not observed any issues in validation or simulation as a result of this erratum. Workaround: None identified.
  • Page 40 This erratum has not been observed in any commercially available operating system or Implication: application. The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being unsupported in the IA-32 Intel ® Architecture Software Developer's Manual, Volume 3, section 10.12.4, Programming the PAT.
  • Page 41 Refer to the IA-32 Intel® Architecture Software Developer's Manual for the correct way to update page tables. Software that conforms to the Software Developer's Manual will operate correctly.
  • Page 42 HITM snoop results. A system may suffer memory ordering failures if its central agent incorporates coherence Implication: sequencing which depends on full self-invalidation of the cache line associated with (1) BWIL ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...
  • Page 43 Any higher priority architectural event that arrives and is handled while the interim paging event is occurring may see the modified value of CR2. The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not Implication: observed this erratum with any commercially available software.
  • Page 44 Exposure to this problem requires the use of a data write which spans a cache line boundary. This erratum may cause loads to be observed out of order. Intel has not observed this erratum Implication: with any commercially available software or system.
  • Page 45 Due to this erratum the breakpoint condition detected flags may be set incorrectly. Implication: Workaround: None identified. For the steppings affected, see the Summary Tables of Changes. Status: ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...

  • Page 46: Specification Changes

    ® ® Celeron Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel ® Architectures Software Developer’s Manual, Volumes 1, 2-A, 2- B, 3-A, and 3-B All Specification Changes will be incorporated into a future version of the appropriate Celeron processor documentation.

  • Page 47: Specification Clarifications

    The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and Intel Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a RESET, the counter will increment even when the processor is halted by the HLT instruction or the external STPCLK# pin.
  • Page 48 The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time- stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).
  • Page 49 The counter value can be read with the RDTSC instruction. The time-stamp counter and the non-sleep clockticks count may not agree in all cases and for all processors. See Section 10.8 for more information on counter operation. § ® ® Intel Celeron Processor in the 478-Pin Package Specification Update...

  • Page 50: Documentation Changes

    Note: Documentation changes for IA-32 Intel(R) Architecture Software Developer’s Manual volumes 1, 2, and 3 will be posted in a separate document " IA-32 Intel(R) Architecture Software Developer’s Manual Documentation Changes". Please follow the link below to become familiar with this file.

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