Basic Timer Function Description - Samsung S3C9454B User Manual

S3C9454B/F9454B

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a Reset by setting BTCON.7–BTCON.4 to
any value other than "1010B" (The "1010B" value disables the watchdog function). A Reset clears BTCON to
"00H", automatically enabling the watchdog timer function. A Reset also selects the oscillator clock divided by
4096 as the BT clock.
A Reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be
cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a Reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction does occur, a Reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a Reset or when
Stop mode has been released by an external interrupt.
In Stop mode, whenever a Reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of f
When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the
clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, a external power-on Reset or an external interrupt occurs to trigger the Stop mode release
and oscillation starts.
2. If a external power-on Reset occurred, the basic timer counter will increase at the rate of f
external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock
source.
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.
4. When a BTCNT.4 is set, normal CPU operation resumes.
Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release
/4096 (for Reset), or at the rate of the preset clock source (for an external interrupt).
OSC
BASIC TIMER and TIMER 0
/4096. If an
OSC
10-3