Intpnd1 Interrupt Pending Register 1 - Samsung S3C9228 User Manual

S3C9228/P9228_UM_REV1.10
INTPND1
— Interrupt Pending Register 1
Bit Identifier
RESET Value
Read/Write
.7
.6
.5
.4
.3
.2
.1
.0
NOTE: Refer to Page 5-6 to clear any pending bits.
.7 .6
0 0
R/W R/W
P1.3's Interrupt Pending Bit
0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)
P1.2's Interrupt Pending Bit
0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)
P1.1's Interrupt Pending Bit
0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)
P1.0's Interrupt Pending Bit
0 No interrupt pending (when read), clear pending bit (when write)
1 Interrupt is pending (when read)
P0.3's Interrupt Pending Bit
No interrupt pending (when read), Clear pending bit (when write)
0
Interrupt is pending (when read)
1
P0.2's Interrupt Pending Bit
No interrupt pending (when read), Clear pending bit (when write)
0
Interrupt is pending (when read)
1
P0.1's Interrupt Pending Bit
0 No interrupt pending (when read), Clear pending bit (when write)
Interrupt is pending (when read)
1
P0.0's Interrupt Pending Bit
No interrupt pending (when read), Clear pending bit (when write)
0
Interrupt is pending (when read)
1
.5 .4
0 0
R/W R/W R/W
CONTROL REGISTERS
.3 .2 .1
0 0 0
R/W R/W
D6H
.0
0
R/W
4-9