Timer 0 Control Register (T0Con) - Samsung KS86C6004 Manual

BASIC TIMER and TIMER 0

TIMER 0 CONTROL REGISTER (T0CON)

T0CON is located at address D2H, and is read/write addressable.
A reset clears T0CON to '00H'. This sets timer 0 to normal interval match mode, selects an input clock frequency
of f /4096, and disables the timer 0 overflow interrupt and match interrupt. You can clear the timer 0 counter
OSC
at any time during normal operation by writing a "1" to T0CON.3.
The timer 0 overflow interrupt can be enabled by writing a "1" to T0CON.1. When a timer 0 overflow interrupt
occurs and is serviced by the CPU, the pending condition must be cleared by software by writing a "0" to the
timer 0 interrupt pending bit, T0CON.0.
To enable the timer 0 match interrupt, you must write T0CON.1 to "1". To detect an interrupt pending condition,
the application program polls T0CON.0. When a "1" is detected, a timer 0 match/ capture interrupt is pending.
When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0"
to the timer 0 interrupt pending bit, T0CON.0.
MSB .7
Timer 0 input clock selection bits:
00 = f /4096
OSC
01 = f /256
OSC
10 = f /8
OSC
11 = Invalid selection
Timer 0 operating mode selection bits:
00 = Interval match mode
01 = Invalid selection
10 = Invalid selection
11 = Overflow mode
10-6
KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec)
TIMER 0 CONTROL REGISTER (T0CON)
D2H, R/W
.6 .5 .4
Figure 10-4. Timer 0 Control Register (T0CON)
.3 .2 .1
Timer 0 match interrupt enable bit:
0 = Disable match interrupt
1 = Enable match interrupt
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
.0 LSB
Timer 0 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)