Omron SYSMAC C200HS Operation Manual page 464

PC Setup
Word(s) Bit(s)
Interrupt/Refresh Processing (DM 6620 to DM 6622)
The following settings are effective after transfer to the PC the next time operation is started.
DM 6620 00 to 09
10 to 11
12 to 15
DM 6621 00 to 07
08 to 15
DM 6622 00 to 07
08 to 15
DM 6623 to 00 to 15
DM 6644
RS-232C Port Settings (DM 6645 to DM 6649)
The following settings are effective after transfer to the PC.
DM 6645 00 to 07
08 to 11
12 to 15
DM 6646 00 to 07
08 to 15
DM 6647 00 to 15
462
Special I/O Unit cyclic refresh (Bit number corresponds to unit number, PC
Link Units included)
0: Enable cyclic refresh and I/O REFRESH (IORF(97)) from main program
1: Disable (refresh only for I/O REFRESH from interrupt programs)
Disable not valid for normal (C200H) interrupt response or on Slave Racks.
Reserved
Interrupt response
0: Normal (C200H compatible)
1: High-speed (C200HS)
Reserved
Special I/O Unit refresh (PC Link Units included)
00: Enable refresh for all Special I/O Units
01: Disable refresh for all Special I/O Units (but, not valid on Slave Racks)
Scheduled interrupt time unit
00: 10 ms
01: 1 ms
Scheduled interrupt time unit enable
00: Disable (10 ms)
01: Enable
Reserved
Port settings
00: Standard (1 start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps)
01: Settings in DM 6646
Words linked for 1:1 link
0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15
Communications mode
0: Host link; 1: RS-232C; 2: 1-to-1 link slave; 3: 1-to-1 link master;
4: NT (PT) link
Baud rate
00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K
Frame format
Start Length
00: 1 bit 7 bits
01: 1 bit 7 bits
02: 1 bit 7 bits
03: 1 bit 7 bits
04: 1 bit 7 bits
05: 1 bit 7 bits
06: 1 bit 8 bits
07: 1 bit 8 bits
08: 1 bit 8 bits
09: 1 bit 8 bits
10: 1 bit 8 bits
11: 1 bit 8 bits
Transmission delay
0000 to 9999: BCD in ms.
Function
Stop Parity
1 bit Even
1 bit Odd
1 bit None
2 bit Even
2 bit Odd
2 bit None
1 bit Even
1 bit Odd
1 bit None
2 bit Even
2 bit Odd
2 bit None
Appendix E
Default
Enable
---
Normal
---
Enable
10 ms
---
Standard
LR 00 to LR 63
Host Link
1.2 K
1 start bit, 7-bit
data, 1 stop bit,
even parity
0 ms