R-Box Performance Monitoring Events; An Overview; R-Box Events Ordered By Code; Table 2-53. Message Events Derived From The Match/Mask Filters - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Field
DRS.AnyDataC
DRS.DataC_M
DRS.WblData
DRS.WbSData
DRS.WbEData
DRS.AnyResp
DRS.AnyResp9flits
DRS.AnyResp11flits
NCB.AnyMsg9flits
NCB.AnyMsg11flits
NCB.AnyInt
NOTE: Bits 71:16 of the match/mask must be 0 in order to derive these events (except where noted -
see DRS.DataC_M). Also the match/mask configuration register should be set to 0x00210000 (bits 21
and 16 set).
2.6.4

R-BOX Performance Monitoring Events

2.6.4.1

An Overview:

The R-Box events provide information on topics such as: a breakdown of traffic as it flows through each
of the R-Box's ports (NEW_PACKETS_RECV) , raw flit traffic (i.e. FLITS_REC_ERR or FLITS_SENT),
incoming transactions entered into arbitration for outgoing ports (ALLOC_TO_ARB), transactions that
fail arbitration (GLOBAL_ARB_BID_FAIL), tracking status of various queues (OUTPUTQ_NE), etc.
In addition, the R-Box provides the ability to match/mask against ALL flit traffic that leaves the R-Box.
This is particularly useful for calculating link utilization, throughput and packet traffic broken down by
opcode and message class.
2.6.5

R-Box Events Ordered By Code

Table 2-54 summarizes the directly-measured R-Box events.
U P G
ERIES NCORE ROGRAMMING UIDE

Table 2-53. Message Events Derived from the Match/Mask filters

Match Mask
[15:0] [15:0]
0x1C00 0x1F80
0x1C00 0x1FE0
&&
Match Mask
[51:48] [51:48]
0x8
0x1C80 0x1FE0
0x1CA0 0x1FE0
0x1CC0 0x1FE0
0x1C00 0x1E00
0x1C00 0x1F00
0x1D00 0x1F00
0x1800 0x1F00
0x1900 0x1F00
0x1900 0x1F80
UNCORE PERFORMANCE MONITORING
Any Data Response message containing a cache line in
response to a core request. The AnyDataC messages are only
sent to an S-Box. The metric DRS.AnyResp - DRS.AnyDataC
will compute the number of DRS writeback and non snoop
write messages.
Data Response message of a cache line in M state that is
response to a core request. The DRS.DataC_M messages are
&&
only sent to S-Boxes.
0xF
Data Response message for Write Back data where cacheline is
set to the I state.
Data Response message for Write Back data where cacheline is
set to the S state.
Data Response message for Write Back data where cacheline is
set to the E state.
Any Data Response message. A DRS message can be either 9
flits for a full cache line or 11 flits for partial data.
Any Data Response message that is 11 flits in length. An 11
flit DRS message contains partial data. Each 8 byte chunk
contains an enable field that specifies if the data is valid.
Any Non Data Response completion message. A NDR message
is 1 on flit.
Any Non-Coherent Bypass message that is 9 flits in length. A
9 flit NCB message contains a full 64 byte cache line.
Any Non-Coherent Bypass message that is 11 flits in length.
An 11 flit NCB message contains either partial data or an
interrupt. For NCB 11 flit data messages, each 8 byte chunk
contains an enable field that specifies if the data is valid.
Any Non-Coherent Bypass interrupt message. NCB interrupt
messages are 11 flits in length.
Description
2-87