B-Box Pmon State - Counter/Control Pairs + Filters; Table 2-17. B_Msr_Pmon_Global_Ctl Register - Field Definitions; Table 2-18. B_Msr_Pmon_Global_Status Register - Field Definitions; Table 2-19. B_Msr_Pmon_Global_Ovf_Ctl Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-17. B_MSR_PMON_GLOBAL_CTL Register – Field Definitions
Field
ctr_en
Table 2-18. B_MSR_PMON_GLOBAL_STATUS Register – Field Definitions
Field
ov
Table 2-19. B_MSR_PMON_GLOBAL_OVF_CTL Register – Field Definitions
Field
clr_ov
2.4.3.2

B-Box PMON state - Counter/Control Pairs + Filters

The following table defines the layout of the B-Box performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter. Setting the .ev_sel field performs the event selection. The .en bit which much be set to 1 to
enable counting.
Additional control bits include:
- .pmi_en governs what to do if an overflow is detected.
NOTE: In the B-Box, each control register can only select from a specific set of events (see
"Performance Monitor Events for B-Box Events"
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
3:0 0 Must be set to enable each B-Box counter (bit 0 to enable ctr0, etc)
NOTE: U-Box enable and per counter enable must also be set to fully
enable the counter.
HW
Bits Reset
Val
3:0 0 If an overflow is detected from the corresponding B-Box PMON register,
it's overflow bit will be set.
NOTE: This bit is also cleared by setting the corresponding bit in
B_MSR_PMON_GLOBAL_OVF_CTL
HW
Bits Reset
Val
3:0 0 Write '1' to reset the corresponding B_MSR_PMON_GLOBAL_STATUS
overflow bit.
for the mapping).
UNCORE PERFORMANCE MONITORING
Description
Description
Description
Table 2-24,
2-31