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I
® X
® P
7500 S
NTEL
EON
ROCESSOR
Field
ig
wrq_empty
rdq_empty
wrq_full
rdq_full
lat_cnt_en
fvid
The ISS subcontrol register contains bits to specify subevents for the ISS_EV (by Intel SMI frame),
CYCLES_SCHED_MODE (cycles spent per ISS mode) and PLD_DRAM_EV (DRAM commands broken
down by scheduling mode in the ISS) events.
Field
ig
sched_mode_pld_trig
sched_mode
frm_type
U
P
G
ERIES
NCORE
ROGRAMMING
UIDE
Table 2-73. M_MSR_PMU_DSP Register – Field Definitions
HW
Bits
Reset
Val
63:11
0
Read zero; writes ignored. (?)
10
0
Generate DSP_FILL trigger when write queue is empty
9
0
Generate DSP_FILL trigger when read queue is empty
8
0
Generate DSP_FILL trigger when write queue is full
7
0
Generate DSP_FILL trigger when read queue is full
6
0
Latency count mode. If 1, the latency for this FVID is counted.
5:0
0
FVID (Fill Victim Index) of transaction for which scheduler latency is to
be counted. Only fully completed transactions are counted.
Table 2-74. M_CSR_ISS_PMU Register – Field Definitions
Bits
Access
31:10
9:7
RW
6:4
RW
3:0
RW
UNCORE PERFORMANCE MONITORING
Description
HW
Reset
Val
Reads 0; writes ignored.
0
Selects the scheduling mode for which the number of
DRAM commands is counted in MA_PLD. Here for
implementation reasons.
Uses same encodings as M_MSR_PMU_ISS.sched_mode:
000: trade-off
001: rd priority
010: wr priority
011: adaptive
0
Selects the scheduling mode for which time-in-mode is
counted.
000: trade-off
001: rd priority
010: wr priority
011: adaptive
0
Selects the frame type to be counted.
0000 - 3CMD - Count all 3-command Intel SMI
frames
0001 - WDAT - Count all write data frames.
0010 - SYNC - Count all SYNC frames.
0011 - CHNL - Count all channel command
frames.
0101 - 0100 - RSVD
1000 - NOP - Count all NOP frames. For
post-silicon debug
1001-1011 - RSVD
1100 - Count all 1-command Intel SMI
frames.
1101-1111 - RSVD
Reset Type
2-104
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