Reading The Sample Interval; Enabling A New Sample Interval From Frozen Counters - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
d) Enable counting at the box-level:
Enable counters within that box via it's 'GLOBAL_CTL' register
i.e. set B_MSR_PMON_GLOBAL_CTL[3] to 1.
e) Select how to gather data. If polling, skip to 4. If sampling:
To set up a sample interval, software can pre-program the data register with a value of [2^48 -
sample interval length]. Doing so allows software, through use of the pmi mechanism, to be notified
when the number of events in the sample have been captured. Capturing a performance monitoring
sample every 'X cycles' (the fixed counter in the W-Box counts uncore clock cycles) is a common use of
this mechanism.
i.e. To stop counting and receive notification when the 1,000th SNP_MERGE has been detected,
- set B_MSR_PMON_CNT to (2^48- 1000)
- set B_MSR_PMON_EVT_SEL.pmi_en to 1
- set U_MSR_PMON_GLOBAL_CTL.frz_all to 1
- set U_MSR_PMON_GLOBAL_CTL.pmi_core_sel to which core the monitoring thread is executing on.
f) Enable counting at the global level by setting the U_MSR_PMON_GLOBAL_CTL.en_all bit to 1. Set the
.rst_all field to 0 with the same write.
And with that, counting will begin.
2.1.3

Reading the Sample Interval

Software can either poll the counters whenever it chooses, or wait to be notified that a counter has
overflowed (by receiving a PMI).
a) Polling - before reading, it is recommended that software freeze and disable the counters (by
clearing U_MSR_PMON_GLOBAL_CTL.en_all).
b) Frozen counters - If software set up the counters to freeze on overflow and send notification when it
happens, the next question is: Who caused the freeze?
Overflow bits are stored hierarchically within the Intel Xeon Processor 7500 Series uncore. First,
software should read the U_MSR_PMON_GLOBAL_STATUS.ov_* bits to determine whether a U or W box
counter caused the overflow or whether it was a counter in a box attached to the S0 or S1 Box.
The S-Boxes aggregate overflow bits from the M/B/C/R boxes they are attached to. So the next step is
to read the S{0,1}_MSR_PMON_SUMMARY.ov_* bits. Once the box(es) that contains the overflowing
counter is identified, the last step is to read that box's *_MSR_PMON_GLOBAL_STATUS.ov field to find
the overflowing counter.
Note: More than one counter may overflow at any given time.
2.1.4

Enabling a New Sample Interval from Frozen Counters

Note: Software can determine if the counters have been frozen due to a PMI by examining two
bits: U_MSR_PMON_GLOBAL_SUMMARY.pmi should be 1 and
U_MSR_PMON_GLOBAL_CTL.en_all should be 0. If not, set
U_MSR_PMON_GLOBAL_CTL.en_all to 0 to disable counting.
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ERIES NCORE ROGRAMMING UIDE
UNCORE PERFORMANCE MONITORING
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