M-Box Pmu Filter Registers; M-Box Pmu Subcontrol Registers - Subunit Descriptions; Table 2-69. M_Msr_Pmu_Timestamp_Unit Register - Field Definitions; Table 2-70. M_Msr_Pmu_Mm_Cfg Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Table 2-69. M_MSR_PMU_TIMESTAMP_UNIT Register – Field Definitions
Field
timestamp
2.7.4.3

M-Box PMU Filter Registers

The M-Box also provides a limited ability to perform address matching for PLD events. The following 3
tables contain the field definitions for the configuration registers governing the M-Box's address match/
mask facility.
Field
enable
ig
Table 2-71. M_MSR_PMU_ADDR_MATCH Register – Field Definitions
Field
ig
address
Table 2-72. M_MSR_PMU_ADDR_MASK Register – Field Definitions
Field
ig
address
2.7.4.4

M-Box PMU Subcontrol Registers - Subunit descriptions

The following Tables contain information on how to program the various subcontrol registers contained
within the M-Box which include the DSP, ISS, MAP, THR, PGT, PLD and FVC registers. The subcontrol
registers govern events coming from subunits within the M-Box which can be roughly categorized as
follows:
MAP - Memory Mapper - receives read and write commands/addresses from the B-Box and translates
the received addresses (physical) into DRAM addresses (rank, bank, row and column). The commands
and translated addresses are sent to the PLD. In parallel, the broken DRAM addresses are also sent to
the PGT.
PLD - Payload Queue - Receives command and translated addresses from the MAP while the PGT
translates MAP commands into DRAM command combinations.
U P
ERIES NCORE ROGRAMMING
HW
Bits Reset
Val
15:0 0 Timestamp is updated every timestamp_unit MClk's
Table 2-70. M_MSR_PMU_MM_CFG Register – Field Definitions
HW
Bits Reset
Val
63 0 Enable debug mode (disables PMON mode).
62:0 0 Read zero; writes ignored. (?)
HW
Bits Reset
Val
63:34 0 Read zero; writes ignored. (?)
33:0 0 34b match address for PLD events
HW
Bits Reset
Val
63:28 0 Read zero; writes ignored. (?)
27:0 0 Address bits to mask 'don't care' bits during match - cache aligned
address 33:6
G
UIDE
Description
Description
Description
Description
UNCORE PERFORMANCE MONITORING
2-102