M-Box Pmu - Overflow, Freeze And Unfreeze - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S U P G UNCORE PERFORMANCE MONITORING
NTEL EON ROCESSOR ERIES NCORE ROGRAMMING UIDE
For instance, to count (in counter 0) the number of RAS DRAM commands
(PLD_DRAM_EV.DRAM_CMD.RAS) that have been issued, set up is as follows:
M_MSR_PMU_CNT_CTL_0.en [0] = 1
M_MSR_PMU_CNT_CTL_0.count_mode [3:2] = 0x0
M_MSR_PMU_CNT_CTL_0.flag_mode [7] = 0
M_MSR_PMU_CNT_CTL_0.inc_sel [13:9] = 0xa
M_MSR_PMU_PLD.cmd [0] = 0x0
M_MSR_PMU_PLD.dram_cmd [12:8] = 0x2
To count (in counter 2) the number of read commands from the B-Box in the scheduler queue
(BCMD_SCHEDQ_OCCUPANCY.READS), set up is as follows:
M_MSR_PMU_CNT_CTL_2.en [0] = 1
M_MSR_PMU_CNT_CTL_0.count_mode [3:2] = 0x0
M_MSR_PMU_CNT_CTL_0.flag_mode [7] = 1
M_MSR_PMU_CNT_CTL_0.inc_sel [21:19] = 0x06
M_MSR_PMU_MAP.cmd [8:5] = 0x0
M_MSR_PMU_MAP.fvid [3:0] = selected Fill Victim Index to track
2.7.3.2

M-Box PMU - Overflow, Freeze and Unfreeze

If an overflow is detected from an M-Box performance counter, the overflow bit is set at the box level
(M_MSR_PMON_GLOBAL_STATUS.ov), and forwarded up the chain towards the U-Box. If a M-Box0
counter overflows, a notification is sent and stored in S-Box0 (S_MSR_PMON_SUMMARY.ov_mb) which,
in turn, sends the overflow notification up to the U-Box (U_MSR_PMON_GLOBAL_STATUS.ov_s0). Refer
to Table 2-26, "S_MSR_PMON_SUMMARY Register Fields" to determine how each M-Box's overflow bit is
accumulated in the attached S-Box.
HW can be also configured (by setting the corresponding .pmi_en to 1) to send a PMI to the U-Box
when an overflow is detected. The U-Box may be configured to freeze all uncore counting and/or send a
PMI to selected cores when it receives this signal.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in M_MSR_PMON_GLOBAL_OVF_CTL.clr_ov. Assuming
all the counters have been locally enabled (.en bit in data registers meant to monitor events) and the
overflow bit(s) has been cleared, the M-Box is prepared for a new sample interval. Once the global
controls have been re-enabled (Section 2.1.4, "Enabling a New Sample Interval from Frozen
Counters"), counting will resume.
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