Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 54

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OPCODE_IN_MATCH
• Title: Opcode In Match
• Category: Mask/Match
• Event Code: 0x03, Max. Inc/Cyc: 1, PERF_CTL: 1,
• Definition: Opcode Match at B-Box Input. Use B_MSR_MATCH/MASK_REG
OPCODE_OUT_MATCH
• Title: Opcode Out Match
• Category: Mask/Match
• Event Code: 0x04, Max. Inc/Cyc: 1, PERF_CTL: 1,
• Definition: Opcode Match at B-Box Output. Use B_MSR_MATCH/MASK_REG
RBOX_VNA_UNAVAIL
• Title: R-Box VNA Unavailable
• Category: R-Box Interface
• Event Code: 0x15, Max. Inc/Cyc: 1, PERF_CTL: 3,
• Definition: Number of times R-Box VNA credit was not available when needed.
SBOX_VN0_UNAVAIL
• Title: S-Box VN0 Unavailable
• Category: S-Box Interface
• Event Code: 0x14, Max. Inc/Cyc: 1, PERF_CTL: 3,
• Definition: Number of times S-Box VN0 credit was not available when needed.
SNPOQ_INSERTS
• Title: SNPOQ Inserts
• Category: ARB Queues
• Event Code: 0x12, Max. Inc/Cyc: 1, PERF_CTL: 1,
• Definition: SNP Output Queue Inserts. Queue Depth is 256.
SNPOQ_OCCUPANCY
• Title: SNPOQ Occupancy
• Category: ARB Queues
• Event Code: 0x12, Max. Inc/Cyc: 1, PERF_CTL: 0,
• Definition: SNP Output Queue Occupancy. Queue Depth is 256.
TF_ALL
• Title: TF Occupancy - All
• Category: Tracker File
• Event Code: 0x04, Max. Inc/Cyc: 1, PERF_CTL: 0,
• Definition: Tracker File occupancy for all requests. Accumulates lifetimes of all memory transactions
that have arrived in this B-Box (TF starts tracking transactions before they are sent to the M-Box).
• NOTE: This event captures overflows from a subcounter tracking all requests. Multiply by 256 to
determine the correct count.
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