Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 70

I ® X ® P 7500 S U P G UNCORE PERFORMANCE MONITORING
NTEL EON ROCESSOR ERIES NCORE ROGRAMMING UIDE
FLITS_SENT_DRS
• Title: DRS Flits Sent to System
• Category: System Bound Transmission
• Event Code: 0x65, Max. Inc/Cyc: 1,
• Definition: Number of data response flits the S-Box has transmitted to the system.
FLITS_SENT_NCB
• Title: NCB Flits Sent to System
• Category: System Bound Transmission
• Event Code: 0x69, Max. Inc/Cyc: 11,
• Definition: Number of non-coherent bypass flits the S-Box has transmitted to the system.
FLITS_SENT_NCS
• Title: NCS Flits Sent to System
• Category: System Bound Transmission
• Event Code: 0x67, Max. Inc/Cyc: 1,
• Definition: Number of non-coherent standard flits the S-Box has transmitted to the system.
HALFLINE_BYPASS
• Title: Half Cacheline Bypass
• Category: Ring Bound Enhancement
• Event Code: 0x30, Max. Inc/Cyc: 1,
• Definition: Half Cacheline Bypass optimization (where the line is sent early) was utilized.
NO_CREDIT_AD
• Title: AD Ring Credit Unavailable
• Category: Ring Bound Credits
• Event Code: 0x87, Max. Inc/Cyc: 1,
• Definition: Number of times the S-Box has a pending SNP, NCS or NCB message to send and there is
no credit for the target egress FIFO.
NO_CREDIT_AK
• Title: AK Ring Credit Unavailable
• Category: Ring Bound Credits
• Event Code: 0x88, Max. Inc/Cyc: 1,
• Definition: Number of times the S-Box has a pending NDR or S2C credit return message to send but
there is no credit for the target egress FIFO.
NO_CREDIT_BL
• Title: BL Ring Credit Unavailable
• Category: Ring Bound Credits
• Event Code: 0x89, Max. Inc/Cyc: 1,
• Definition: Number of times the S-Box has a pending DRS or debug message to send and there is no
credit for the target egress FIFO.
NO_CREDIT_DRS
• Title: DRS Credit Unavailable
• Category: System Bound Credits
• Event Code: 0x82, Max. Inc/Cyc: 1,
• Definition: Number of times the S-Box has a pending data response message to send and there is no
DRS or VNA credit available.
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