C-Box Pmon State - Counter/Control Pairs; Table 2-10. C_Msr_Pmon_Global_Ctl Register - Field Definitions; Table 2-11. C_Msr_Pmon_Global_Status Register - Field Definitions; Table 2-12. C_Msr_Pmon_Global_Ovf_Ctl Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
If an overflow is detected from one of the C-Box PMON registers, the corresponding bit in the
_GLOBAL_STATUS.ov field will be set. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a
user must set the corresponding bits in the _GLOBAL_OVF_CTL.clr_ov field before beginning a new
sample interval.
Table 2-10. C_MSR_PMON_GLOBAL_CTL Register – Field Definitions
Field
ctr_en
Table 2-11. C_MSR_PMON_GLOBAL_STATUS Register – Field Definitions
Field
ov
Table 2-12. C_MSR_PMON_GLOBAL_OVF_CTL Register – Field Definitions
Field
clr_ov
2.3.3.2

C-Box PMON state - Counter/Control Pairs

The following table defines the layout of the C-Box performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter. Setting the .ev_sel and .umask fields performs the event selection. The .en bit must be set to
1 to enable counting.
Additional control bits include:
- .pmi_en governs what to do if an overflow is detected.
- .threshold - since C-Box counters can increment by a value greater than 1, a threshold can be applied.
If the .threshold is set to a non-zero value, that value is compared against the incoming count for that
event in each cycle. If the incoming count is >= the threshold value, then the event count captured in
the data register will be incremented by 1.
- .invert - Changes the .threshold test condition to '<'
- .edge_detect - Rather than accumulating the raw count each cycle (for events that can increment by
1 per cycle), the register can capture transitions from no event to an event incoming.
U P G
ERIES NCORE ROGRAMMING UIDE
HW
Bits Reset
Val
5:0 0 Must be set to enable each C-Box counter.
NOTE: U-Box enable and per counter enable must also be set to fully
enable the counter.
HW
Bits Reset
Val
5:0 0 If an overflow is detected from the corresponding CBOX PMON register,
it's overflow bit will be set.
NOTE: This bit is also cleared by setting the corresponding bit in
C_MSR_PMON_GLOBAL_OVF_CTL
HW
Bits Reset
Val
5:0 0 Write '1' to reset the corresponding C_MSR_PMON_GLOBAL_STATUS
overflow bit.
UNCORE PERFORMANCE MONITORING
Description
Description
Description
2-14