Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 115

I ® X ® P 7500 S U P G UNCORE PERFORMANCE MONITORING
NTEL EON ROCESSOR ERIES NCORE ROGRAMMING UIDE
Original B-Box transaction's FVID sent from DSP during subcommand execution where the appropriate
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subcommand information is accessed to compose the Intel SMI command frame.
PGT - Page Table - Keeps track of open pages. Translates the read/write commands into DRAM
command combinations (i.e. PRE, RAS, CASrd, CASwr). The generated command combination (e.g.
PRE_RAS_CASrd) is then sent to the Dispatch Queue.
If
a) there is already a command in the DSP for a particular DIMM (rank/bank)
b) the DSP's readQ or writeQ is full
c) if a rank requires thermal throttling because the DIMM is heating up
d) or a refresh is executing to a rank.
Then the PGT will detect the conflict and place the command in the retryQ for later execution.
DSP - Dispatch Queue - receives DRAM command from PGT and stores request in a read or write
subqueue. In the dispatch queue, the command combinations are broken up into subcommand kinds
that are sequenced in the necessary order required to complete the read/write transaction (i.e. PRE,
RAS, CAS, CASpre). All "ready to execute" subcommands stored within the various DSP queues are
presented simultaneously to the issue logic.
Once the ISS returns the subcommand choice, the oldest DSP entry containing that subcommand kind
(for a particular DIMM) is allowed to execute. During subcommand execution, the DSP sends the
original (B-Box) transaction's FVID (that was stored in the DSP entry) to the PLD. After subcommand
execution, the DSP's queue entry state is updated to the next required subcommand kind (based on the
original command combination) to be executed (new state).
ISS - Issue - receives "ready to execute" subcommands from the dispatch queue(s) as a bit vector that
is organized with each bit representing a subcommand kind per DIMM (i.e. RAS for DIMM0, CAS for
DIMM3). Having an overview of all these subcommand kinds enables the ISS to flexibly schedule/
combine subcommands out-of-order. Once a subcommand kind for a particular DIMM is selected from
the issue vector by the ISS, that subcommand choice is driven back to the DSP
THR - Thermal Throttling
FVC - Fill and Victim Control - drives all the control signals required by the fill datapath and victim
datapath. Additionally, it handles issuing and control of the buffer maintenance commands (i.e. MRG,
F2V, V2V, V2F and F2B). It also contains the logic to respond to the B-Box when commands in the M-
Box have completed.
The DSP subcontrol register contains bits to specify subevents of the DSP_FILL event, breaking it into
write queue/read queue occupancy as well as DSP latency.
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