Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 49

I ® X ® P 7500 S U P G UNCORE PERFORMANCE MONITORING
NTEL EON ROCESSOR ERIES NCORE ROGRAMMING UIDE
COHQ_IMT_ALLOC_WAIT
• Title: COHQ IMT Allocation Wait
• Category: ARB Queues
• Event Code: 0x13, Max. Inc/Cyc: 1, PERF_CTL: 3,
• Definition: Cycles Coherence Queue Waiting on IMT Allocation.
DIRQ_INSERTS
• Title: DIRQ Inserts
• Category: ARB Queues
• Event Code: 0x17, Max. Inc/Cyc: 1, PERF_CTL: 1,
• Definition: Directory Queue Inserts. Queue Depth is 256.
DIRQ_OCCUPANCY
• Title: DIRQ Occupancy
• Category: ARB Queues
• Event Code: 0x17, Max. Inc/Cyc: 1, PERF_CTL: 0,
• Definition: Directory Queue Occupancy. Queue Depth is 256.
DEMAND_FETCH
• Title: Demand Fetches
• Category: Miscellaneous
• Event Code: 0x0F, Max. Inc/Cyc: 1, PERF_CTL: 3,
• Definition: Counts number of times a memory access was issued after CohQ pop (i.e. IMT prefetch
was not used).
DRSQ_INSERTS
• Title: DRSQ Inserts
• Category: ARB Queues
• Event Code: 0x09, Max. Inc/Cyc: 1, PERF_CTL: 1,
• Definition: DRSQ Inserts.
DRSQ_OCCUPANCY
• Title: DRSQ Occupancy
• Category: ARB Queues
• Event Code: 0x09, Max. Inc/Cyc: 1, PERF_CTL: 0,
• Definition: DRSQ Occupancy. Queue Depth is 4.
EARLY_ACK
• Title: Early ACK
• Category: Miscellaneous
• Event Code: 0x02, Max. Inc/Cyc: 1, PERF_CTL: 3,
• Definition: M-Box Early Acknowledgements.
IMPLICIT_WBS
• Title: Implicit WBs
• Category: Miscellaneous
• Event Code: 0x12, Max. Inc/Cyc: 1, PERF_CTL: 3,
• Definition: Number of Implicit Writebacks.
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