Intel ® 7500 Scalable Memory Buffer; M-Box Performance Monitoring Overview; Choosing An Event To Monitor - Example Using Subcontrol Registers - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
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2.7.2.1 Intel 7500 Scalable Memory Buffer
The Intel Xeon Processor 7500 Series supports Intel
channels.
• Intel SMI protocol and signalling includes support for the following:
— 4.8 Gbs, 6.4 Gbs signalling
— forwarded clock fail-over NB and SB.
— 9 data lanes plus 1 CRC lane plus 1 spare lane SB.
— 12 data lanes plus 1 CRC lane plus 1 spare NB.
— Support for integrating RDIMM thermal sensor information into Intel
• No support for daisy chaining (Intel 7500 Scalable Memory Buffer is the only Intel SMI device in the
channel).
• No support for FB-DIMM1 protocol and signaling.
The Intel 7500 Scalable Memory Buffer provides an interface to DDR3 DIMMs and supports the
following DDR3 functionality:
• DDR3 protocol and signalling, includes support for the following:
— Up to two RDIMMs per DDR3 bus
— Up to eight physical ranks per DDR3 bus (sixteen per Intel 7500 Scalable Memory Buffer)
— 800 MT/s or 1066 MT/s (both DDR3 buses must operate at the same frequency)
— Single Rank x4, Dual Rank x4, Single Rank x8, Dual Rank x8, Quad Rank x4, Quad Rank x8
— 1 GB, 2 GB, 4 GB, 8 GB, 16 GB DIMM
— DRAM device sizes: 1 Gb, 2 Gb
— Mixed DIMM types (no requirement that DIMMs must be the same type, except that all DIMMs
attached to an Intel 7500 Scalable Memory Buffer must run with a common frequency and core
timings. Host lockstep requirements may impose additional requirements on DIMMs on
separate Intel SMI channels).
— DDR buses may contain different number of DIMMs, zero through two. (Host lockstep
requirements may impose additional requirements on DIMMs on separate Intel SMI channels).
— Cmd/Addr parity generation and error logging.
• No support for non-ECC DIMMs
• No support for DDR2 protocol and signaling
• Support for integrating RDIMM thermal sensor information into Intel SMI Status Frame.
2.7.3

M-Box Performance Monitoring Overview

Each M-Box supports performance monitoring through 6 48-bit wide counters (M_MSR_PMU_CNT_{5-
0}). Each of these counters can be configured to monitor any available event through its companion
control register. However, a good chunk of the generic events defer configuration to various subcontrol
registers (as detailed below). Since there are a limited number of control registers, software must pay
attention to various restrictions as to what events may be counted simultaneously. The M-Box counters
increment by a maximum of 1 per cycle.
For information on how to setup a monitoring session, refer to
Monitoring Control".
2.7.3.1

Choosing An Event To Monitor - Example using subcontrol registers

As has been stated, monitoring a particular event often requires configuring auxiliary MSRs.
U P G
ERIES NCORE ROGRAMMING UIDE
UNCORE PERFORMANCE MONITORING
®
7500 Scalable Memory Buffers on the Intel
Section 2.1, "Global Performance
®
SMI
®
SMI Status Frame.
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