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I
® X
® P
7500 S
NTEL
EON
ROCESSOR
2.7
M-Box Performance Monitoring
2.7.1
Overview of the M-Box
The memory controller interfaces to the Intel
write commands into specific Intel
based on the FB-DIMM architecture, but the Intel 7500 Scalable Memory Buffer is not an AMB2 device
and has significant exceptions to the FB-DIMM2 architecture. The memory controller also provides a
variety of RAS features, such as ECC, memory scrubbing, thermal throttling, mirroring, and DIMM
sparing. Each socket has two independent memory controllers, and each memory controller has two
Intel SMI channels that operate in lockstep.
2.7.2
Functional Overview
The memory controller is the interface between the home node controller (B-Box) and the Intel
Scalable Memory Interconnect and basically translates read and write commands into specific memory
commands and schedules them with respect to memory timing. The other main function of the memory
controller is advanced ECC support. There are two memory controllers per socket, each controlling two
Intel SMI channels in lockstep. Because of the data path affinity to the B-Box data path, each B-Box is
paired with a memory controller, that is, B-Boxes and memory controllers come in pairs.
scheduler
Bbox
cmd
data path
Bbox
data
Bbox
ack
data
to
Bbox
The memory controller interfaces to the router through the B-Box (home node coherence controller)
and to the P-Box pads.
U
P
ERIES
NCORE
ROGRAMMING
®
®
Scalable Memory Interconnect (Intel
mapper
accu
byte
victim
mula
mer
buffer
tor
ge
deacc
fill
umula
buffer
tor
Figure 2-2. Memory Controller Block Diagram
G
UIDE
7500 Scalable Memory Buffers and translates read and
page
table
dispatch
queue
retry
queue
payload queue
ECC
err
gen
inject
control logic
ECC check
UNCORE PERFORMANCE MONITORING
®
SMI) operations. Intel SMI is
DRAM
command
issue
and
timing
FBD
FBD
packe
CRC
tizer
gen
FBD
FBD
depack
CRC
etizer
check
Intel®
SMI
Frame
Intel®
SMI
Frame
2-95
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