C-Box Box Level Pmon State - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
CB4_CR_C_MSR_PMON_CTR_3
CB4_CR_C_MSR_PMON_EVT_SEL_3
CB4_CR_C_MSR_PMON_CTR_2
CB4_CR_C_MSR_PMON_EVT_SEL_2
CB4_CR_C_MSR_PMON_CTR_1
CB4_CR_C_MSR_PMON_EVT_SEL_1
CB4_CR_C_MSR_PMON_CTR_0
CB4_CR_C_MSR_PMON_EVT_SEL_0
CB4_CR_C_MSR_PMON_GLOBAL_OVF_CT
L
CB4_CR_C_MSR_PMON_GLOBAL_STATUS
CB4_CR_C_MSR_PMON_GLOBAL_CTL
CB0_CR_C_MSR_PMON_CTR_5
CB0_CR_C_MSR_PMON_EVT_SEL_5
CB0_CR_C_MSR_PMON_CTR_4
CB0_CR_C_MSR_PMON_EVT_SEL_4
CB0_CR_C_MSR_PMON_CTR_3
CB0_CR_C_MSR_PMON_EVT_SEL_3
CB0_CR_C_MSR_PMON_CTR_2
CB0_CR_C_MSR_PMON_EVT_SEL_2
CB0_CR_C_MSR_PMON_CTR_1
CB0_CR_C_MSR_PMON_EVT_SEL_1
CB0_CR_C_MSR_PMON_CTR_0
CB0_CR_C_MSR_PMON_EVT_SEL_0
CB0_CR_C_MSR_PMON_GLOBAL_OVF_CT
L
CB0_CR_C_MSR_PMON_GLOBAL_STATUS
CB0_CR_C_MSR_PMON_GLOBAL_CTL
2.3.3.1

C-Box Box Level PMON state

The following registers represent the state governing all box-level PMUs in the C-Box.
The _GLOBAL_CTL register contains the bits used to enable monitoring. It is necessary to set the
.ctr_en bit to 1 before the corresponding data register can collect events.
U P G
ERIES NCORE ROGRAMMING UIDE
MSR Name
UNCORE PERFORMANCE MONITORING
MSR Size
Acces
Addres (bits
s
s )
RW_R 0xD37 64 C-Box 4 PMON Counter 3
W
RW_RO 0xD36 64 C-Box 4 PMON Event Select 3
RW_R 0xD35 64 C-Box 4 PMON Counter 2
W
RW_RO 0xD34 64 C-Box 4 PMON Event Select 2
RW_R 0xD33 64 C-Box 4 PMON Counter 1
W
RW_RO 0xD32 64 C-Box 4 PMON Event Select 1
RW_R 0xD31 64 C-Box 4 PMON Counter 0
W
RW_RO 0xD30 64 C-Box 4 PMON Event Select 0
WO_R 0xD22 32 C-Box 4 PMON Global Overflow Control
O
RW_R 0xD21 32 C-Box 4 PMON Global Status
W
RW_RO 0xD20 32 C-Box 4 PMON Global Control
RW_R 0xD1B 64 C-Box 0 PMON Counter 5
W
RW_RO 0xD1A 64 C-Box 0 PMON Event Select 5
RW_R 0xD19 64 C-Box 0 PMON Counter 4
W
RW_RO 0xD18 64 C-Box 0 PMON Event Select 4
RW_R 0xD17 64 C-Box 0 PMON Counter 3
W
RW_RO 0xD16 64 C-Box 0 PMON Event Select 3
RW_R 0xD15 64 C-Box 0 PMON Counter 2
W
RW_RO 0xD14 64 C-Box 0 PMON Event Select 2
RW_R 0xD13 64 C-Box 0 PMON Counter 1
W
RW_RO 0xD12 64 C-Box 0 PMON Event Select 1
RW_R 0xD11 64 C-Box 0 PMON Counter 0
W
RW_RO 0xD10 64 C-Box 0 PMON Event Select 0
WO_R 0xD02 32 C-Box 0 PMON Global Overflow Control
O
RW_R 0xD01 32 C-Box 0 PMON Global Status
W
RW_RO 0xD00 32 C-Box 0 PMON Global Control
Description
2-13