Introduction; Uncore Pmu Overview; Figure 1-1. Intel Xeon Processor 7500 Series Block Diagram - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
1.1

INTRODUCTION

Figure 1-1 provides an Intel

Figure 1-1. Intel Xeon Processor 7500 Series Block Diagram

1.2

Uncore PMU Overview

The processor uncore performance monitoring is supported by PMUs local to each of the C, S, B, M, R, U,
and W-Boxes. Each of these boxes communicates with the U-Box which contains registers to control all
uncore PMU activity (as outlined in
All processor uncore performance monitoring features can be accessed through RDMSR/WRMSR instruc-
tions executed at ring 0.
Since the uncore performance monitors represent socket-wide resources that are not context switched
by the OS, it is highly recommended that only one piece of software (per-socket) attempt to program and
extract information from the monitors. To keep things simple, it is also recommended that the monitoring
software communicate with the OS such that it can be executed on coreId = 0, threadId = 0. Although
recommended, this step is not necessary. Software may be notified of an overflowing uncore counter on
any core.
U P G
ERIES NCORE ROGRAMMING UIDE
® ®
Xeon Processor 7500 Series block diagram.
Section 2.1, "Global Performance Monitoring
INTRODUCTION
CHAPTER 1
INTRODUCTION
Control").
1-1