Uncore Pmu Summary Tables; Table 1-1. Per-Box Performance Monitoring Capabilities; Uncore Performance Monitoring Msrs - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
The general performance monitoring capabilities in each box are outlined in the following table.
Box
C-Box
S-Box
B-Box
M-Box
R-Box
U-Box
W-Box
1.3

Uncore PMU Summary Tables

Box
R-Box Counters
R-Box R
R-Box L
C-Box Counters
C-Box 7
C-Box 3
C-Box 5
C-Box 1
C-Box 6
C-Box 2
C-Box 4
C-Box 0
M-Box Counters
U P G
ERIES NCORE ROGRAMMING UIDE

Table 1-1. Per-Box Performance Monitoring Capabilities

# Boxes
8
2
2
2
1 (L/R sides)
1
1
Table 1-2. Uncore Performance Monitoring MSRs
MSR Addresses
0xE3F-0xE30
0xE2F-0xE2C
0xE2B-0xE24
0xE22-0xE20
0xE1F-0xE10
0xE0F-0xE0C
0xE0B-0xE04
0xE02-0xE00
0xDFB-0xDF0
0xDE2-0xDE0
0xDDB-0xDD0
0xDC2-0xDC0
0xDBB-0xDB0
0xDA2-0xDA0
0xD9B-0xD90
0xD82-0xDE0
0xD7B-0xD70
0xD62-0xD60
0xD5B-0xD50
0xD42-0xD40
0xD3B-0xD30
0xD22-0xD20
0xD1B-0xD10
0xD02-0xD00
# Counters/ Generic
Box Counters?
6 Y
4 Y
4 N
6 N
16 N
(2 per port, 8
per side)
1 Y
4 Y
Counter/Config Registers(15-8)
QLX SubConfig Registers for Ports 7-4
IPERF 1 SubConfig Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers(7-0)
QLX SubConfig Registers for Ports 3-0
IPERF 0 SubConfig Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
Counter/Config Registers
Global (Control/Status/Ovf Control)
INTRODUCTION
Packet Match/
Bit Width
Mask Filters?
N 48
Y 48
Y 48
N 48
Y 48
N 48
N 48
Description
1-2