Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 103

I ® X ® P 7500 S
NTEL EON ROCESSOR
GLOBAL_ARB_BID_FAIL
• Title: Failed Global ARB Bids
• Category: QLX
• [Bit(s)] Value: [3:0]0x5, Max. Inc/Cyc: 1,
• Definition: Number of bids for output port that were rejected at the global ARB.
Extension
VN0.HOM
VN0.SNP
VN0.NDR
VN0.NCS
VN0.DRS
VN0.NCB
---
VN1.HOM
VN1.SNP
VN1.NDR
VN1.NCS
VN1.DRS
VN1.NCB
---
INQUE_READ_WIN
• Title: Input Queue Read Win.
• Category: RIX
• [Bit(s)] Value: [8]0x1, Max. Inc/Cyc: 1,
• Definition: Bid wins arbitration. Counts number of IQA reads and drains to XBAR.
LOCAL_ARB_BID
• Title: Local ARB Bids
• Category: QLX
• [Bit(s)] Value: [3:0]0x1, Max. Inc/Cyc: 1,
• Definition: Number of clocks of non-zero Local ARB Bids.
LOCAL_ARB_BID_FAIL
• Title: Failed Local ARB Bids
• Category: QLX
• [Bit(s)] Value: [3:0]0x4, Max. Inc/Cyc: 1,
• Definition: Number of clocks of non-zero Local ARB Bids that were rejected.
U P G
ERIES NCORE ROGRAMMING UIDE
Table 2-58. Unit Masks for GLOBAL_ARB_BID_FAIL
QLX_EVENT
_CFG Bit
Values
[7:4]
b0000
b0001
b0010
b0011
b0100
b1001
b0110-b0111
b1000
b1001
b1010
b1011
b1100
b1101
b1110-b1111
UNCORE PERFORMANCE MONITORING
Description
VN0 Home Messages
VN0 Snoop Messages
VN0 Non-Data Response Messages
VN0 Non-Coherent Standard Messages
VN0 Data Response Messages
VN0 Non-Coherent Bypass Messages
(*illegal selection*)
VN1 Home Messages
VN1 Snoop Messages
VN1 Non-Data Response Messages
VN1 Non-Coherent Standard Messages
VN1 Data Response Messages
VN1 Non-Coherent Bypass Messages
(*illegal selection*)
2-91