R-Box Qlx Performance Monitoring Control Registers; Table 2-49. R_Msr_Port{7-0}_Qlx_Cfg Register Fields - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Field
IQA_READ_OK
NEW_PVN
NEW_PC
2.6.3.5

R-Box QLX Performance Monitoring Control Registers

The following table contains the events that can be monitored if one of the ARB registers was chosen to
select the event.
Field
ig
ev1_sub
ev1_cls
U P G
ERIES NCORE ROGRAMMING UIDE
Table 2-48. R_MSR_PORT{7-0}_IPERF_CFG{1-0} Registers (Sheet
HW
Bits Reset
Val
8 0x0 Bid wins arbitration. Read flit from IQA and drains to XBAR.
7:6 0x0 New Packet VN Select: Anded with result of New Packet Class Bit
Mask.
11: VNA | VN1 | VN0
10: VNA
01: VN1
00: VN0
5:0 0x0 New Packet Class Bit Mask: Bit mask to select which packet types to
count. Anded with New Packet VN Select.
b1XXXXX: Snoop
bX1XXXX: Home
bXX1XXX: Non-Data Response
bXXX1XX: Data Response
bXXXX1X: Non-Coherent Standard
bXXXXX1: Non-Coherent Bypass
Table 2-49. R_MSR_PORT{7-0}_QLX_CFG Register Fields (Sheet 1
HW
Bits Reset
Val
31:16 Read zero; writes ignored.
15 0x0 Performance Event 1 Sub-Class Select:
0: VN0
1: VN1
14:12 0x0 Performance Event 1 Class Select:
000: HOM
001: SNP
010: NDR
011: NCS
100: DRS
101: NCB
110: VNA - Small
111: VNA - Large
UNCORE PERFORMANCE MONITORING
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Description
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Description
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