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I
® X
® P
7500 S
NTEL
EON
ROCESSOR
Table 2-100. W_MSR_PMON_CTR_{3-0} Register – Field Definitions
Field
event_count
Table 2-101. W_MSR_PMON_FIXED_CTR Register – Field Definitions
Field
event_count
Note:
Due to an errata found within the Intel Xeon Processor 7500 Series, SW must consider
two special cases:
• If SW reads a counter whose value ends in 0x000000 or 0x000001, SW should subtract 0x1000000
to get the correct value.
• SW should not set up a sample interval whose value ends in either 0xfffffe or 0xffffff.
2.8.4
W-BOX Performance Monitoring Events
2.8.4.1
An Overview:
The W-Box's primary offering to understanding the impact of the uncore on performance is the fixed
counter. This counter, which increments at the frequency of the uncore clock, can be used to add a time
element to numerous events across the uncore.
Beyond that, the W-Box provides a smattering of events that indicating when, and under what
circumstances, the W-Box throttled the chip due to power constraints.
2.8.5
W-Box Events Ordered By Code
Table 2-102
summarizes the directly-measured W-Box events.
C_THROTTLE_TMP
C_C0_THROTTLE_DIE
PROCHOT
C0_THROTTLE_PROCHOT
C_CYCLES_TURBO
TM1_ON
RATIO_CHANGE_ABORT
2.8.6
W-Box Performance Monitor Event List
This section enumerates Intel Xeon Processor 7500 Series uncore performance monitoring events for
the W-Box.
U
P
ERIES
NCORE
ROGRAMMING
HW
Bits
Reset
Val
47:0
0
48-bit performance event counter
HW
Bits
Reset
Val
47:0
0
48-bit performance event counter
Table 2-102. Performance Monitor Events for W-Box Events
Event
Symbol Name
Code
0x00
0x01
0x02
0x03
0x04
0x07
0x08
G
UIDE
Description
Description
Max
Inc/Cyc
1
Core Throttled due to Temp
1
Core Throttled in C0
1
Prochot
1
Core Throttled in C0 due to FORCEPR
1
Core in C0 at Turbo
1
TM1 Throttling On
1
Ratio Change Abort
UNCORE PERFORMANCE MONITORING
Description
2-128
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